1. Field of the Invention
The present invention relates to an instruction controlling system for allowing out-of-order instruction execution in order to quickly execute instructions in an information processing device and a method thereof.
2. Description of the Related Art
The out-of-order instruction execution method is a method for sequentially executing instructions starting from an instruction whose input data has been provided in an order different from the instruction order directed by a program. The instructions are executed in an arbitrary order, but the resources that can be accessed by the program, such as a storage area, contents of registers, etc. must be updated and referenced in the order directed by the program.
As a technique for ensuring that the contents of registers are updated and referenced in the order directed by the program, a technique for renaming a register can be cited. With a conventional register renaming technique, physical registers whose number is larger than that of logical registers designated according to an architecture are prepared, and the contents of all of the logical registers are mapped to the physical registers, and updated and referenced. The reason why the physical registers whose number is larger than that of the logical registers are arranged is to maintain a physical register corresponding to a logical register even if a pipeline is cleared due to some cause.
FIG. 1 is a schematic diagram showing a conventional register renaming technique.
A register renaming table 901 includes entries whose number is equal to that of logical registers, and each of the entries stores a physical register number corresponding to a logical register number. In FIG. 1, a "D" cycle indicates decoding of an instruction; an "A" cycle indicates an address calculation of a main storage operand; a "T" cycle indicates address conversion; a "B" cycle indicates a read operation of the operand; an "E" cycle indicates arithmetic operation execution; a "C" cycle indicates a checking operation; and a "W" cycle indicates a storage operation of an arithmetic operation result.
FIG. 1 shows the case in which two LOAD instructions interfere with a register (perform processes for an identical physical register address). When the initial LOAD instruction is issued, a logical register address is output from an instruction register 900. In FIG. 1, "R" indicates the logical register address in the instruction register 900. When the logical register address is output from the instruction register 900, the register renaming table 901 is referenced and the physical register address corresponding to the logical register address output from the instruction register 900 is output. When the physical register address is output, the corresponding data is loaded into the physical register storing the physical register address in a physical register file 902 on the "C" cycle and the "W" cycle.
Suppose that the second LOAD instruction is issued after the first LOAD instruction. The second LOAD instruction is an instruction which uses the data written to the physical register with the first LOAD instruction, and causes register interference. When the second LOAD instruction is issued, the logical address is output from the instruction register 900 and converted into a physical register address. This physical register address is the same as that output with the first LOAD instruction. Then, the data is extracted from the physical register in the physical register file 902, and input to an arithmetic unit 903.
According to FIG. 1, the physical register cannot be referenced and read out unless logical register addresses are converted into physical register addresses. As referred to in the explanation about the conventional technique, physical registers (a physical register file) whose number is larger than that of logical registers are prepared in the register renaming technique so as to ensure the update and reference operations in the order directed by a program according to the out-of-order method. Additionally, since the physical registers are used in various processes, the numbers of their entries are large. Accordingly, the number of stages of the physical registers is large. Additionally, both the number of stages of selectors required for reading the data corresponding to the physical registers, and the number of logic circuits for transmitting and receiving the data are large. If the numbers of stages of physical registers and their peripheral logic circuits are large as described above, a data read operation requires a considerable amount of time. As a result, one machine cycle time must be extended. Accordingly, if the renaming table 901 is accessed, a physical register is accessed, the contents of the physical register is read out, and an instruction is transmitted to an arithmetic unit during the instruction decoding cycle, the machine cycle can be possibly delayed. For example, the period of the "D" cycle of the second LOAD instruction becomes 1.5 times the other cycles in FIG. 1.
If a cycle for renaming a register is newly arranged in order to avoid the above described problem, two extra cycles are always required from the instruction decoding cycle to the arithmetic operation execution cycle, which also leads to the degradation of performance.
As described above, the register renaming technique shown in FIG. 1 has the problems that the machine cycle becomes longer (the delay of the machine cycle), the number of cycles until the execution of an arithmetic operation increases, etc., which impede the speed-up of an arithmetic operation.